• Gender: Male
• Age: 43
• Designation: Junior Executive
• Highest Education Level: Post Graduate Diploma
• Preferred Country: India
• Preferred Location: Anywhere
• Work Experience: 16.5 Year(s)

Education

Post Graduate Diploma Vlsi Designing in August-2007 from C-Dac, Pune with 73.66%.

M.Sc. Electronics in April- 2004 from Sardar Patel University with 64.11%.

B.Sc. Electronics in April-2002 from Sardar Patel University with 61.48%.

P.L.C. (Programmable Logic Controllers) programming at HI-TECH TRAINING CENTER, Vadodara.

H.S.C. Science in March-1999 from G.S.E.B. with 47.77%

S.S.C. in March-1997 from G.S.E.B. with 76.29%.

Skill Sets

EDA Tools MODELSIM 6.1, LEONARDO SPECTRUM, XILINX ISE 8.2I, PROTEL (PCB Layout Designing), MICROWIND 3.1.6 (CMOS Layout).
Programming Software / Hardware Description Language VERILOG, VHDL, C, P.L.C. Programming.

Area of Interest:
Advanced Digital Designing, Static Timing Analysis, Synthesis, CMOS.

Work Experience

VLSI Design Engineer
Since October 2007 to till date.
Currently working with a leading company in Western India

Summer Trainee
Worked with INSTITUTE FOR PLASMA RESEARCH (I.P.R.), Bhat, Gandhinagar.

Projects Undertaken:
Project Name:- Serial Peripheral Interface (SPI). (C-DAC Project)
Tools:- MODELSIM SE 5.8c, Leonardo Spectrum.
Platform:- Verilog HDL.
Project Description:-
In this project we implemented the SPI bus to communicate among Master-Slave devices.

Project Responsibilities:-
Verilog HDL coding and optimization.
Final documentation.

Project Name:- Digital Web Printing Machine. ( Global Tech (I) Pvt. Ltd)
Tools:- XILINX 8.2, MODELSIM 6.1, Leonardo Spectrum.
Client:- Alteem Instruments.
Platform:- Verilog HDL.
Project Description:-
In this project controlling of Horizontal and Vertical motor in each unit for proper colour printing on the web (plastic). Total No. of units are 10.

Project Responsibilities:-
Changes in the Verilog code as requests from the client.
Final testing of the system on-site.

Project Name:- Control System. ( Global Tech (I) Pvt. Ltd))
Tools:- XILINX 8.2, MODELSIM 6.1, Leonardo Spectrum.
Client:- IIT, KHARAGPUR.
Platform:- Verilog HDL.
Project Description:-
In this project there are the controlling of 20 stepper motors and 400 solenoids based on the given 20 different programs. This project is implemented by the 1 FPGA and 7 CPLDs.

Project Responsibilities
Architecture understanding of Control Systems modules.
Verilog HDL coding and Synthesis.
Interface design of JTAG, PROM, FPGA,CPLDs and associated components.
Hardware Testing.